webinar register page

Webinar banner
'Optimizing embedded RISC-V hardware/software development from virtual models to in-life silicon instrumentation.'
☕️ Join the latest webinar with RISC-V international members Andes, Imperas, and UltraSoC on the use of virtual platforms and FPGA’s for RISC-V multicore SoCs, covering early SW development, HW verification and analysis for system level design optimization.

Part #1 of our AI & ML webinar series focused on architecture. We are excited for Part #2, as we tackle the key hardware and software prototyping phase including demos with example platforms to test multicore processing elements, the foundational building blocks of AI Inferencing or ML designs. (And stay tuned for Part #3, coming soon!).

⏰ As previously, we will be running the webinar twice; on 15 July 2020, at 8am PDT (4pm BST, 5pm CET, 11pm CST) and 5pm PDT (1am BST, 8am CST on 1 July). Registering will allow you to join at both times. However, it would be helpful if you could indicate by checking one of the boxes below which webinar you intend to join.

The Agenda will cover the key prototype phases of SoC design:

▸ Virtual platforms as early evaluation & demo ‘boards’ - Early software development including debug and verification
▸ Processor cores implemented as FPGA prototypes - Optimized features for Cores and Processor sub-systems
▸ Advanced analytics with FPGA prototypes - Debug & Trace, and On-Chip performance monitors and analytics

[The webinar will conclude with a live hosted Q&A session with all the presenters as a group discussion.]

⇣ Unable to join on the day? Please still register, and you will be sent a recording of the webinar when it is available.
Jul 15, 2020 08:00 AM
Jul 15, 2020 05:00 PM
Time shows in
* Required information
Loading

Speakers

John Min
Director of Field Applications Engineering for North America @Andes Technology
John has been working for processor companies in the Silicon Valley for past 30 years with companies including at Hewlett Packard, LG, ARC, MIPS and SiFive. He brings wealth of information on Architecture of processors, IP and high performance processing. John specializes in balancing the Power, Area and Performance to yield optimized SoC. John is a graduate of University of Southern California with degrees in Electrical Engineering and Biomedical Engineering.
Larry Lapides
Vice President Sales @Imperas Software Limited
Prior to joining Imperas, Larry ran sales at Averant and Calypto Design Systems. He was vice president of worldwide sales during the run-up to Verisity's IPO (the top performing IPO of 2001), and afterwards as Verisity solidified its position as the fifth largest EDA company. Before Verisity and SureFire (acquired by Verisity), Larry held positions in sales and marketing for Exemplar Logic and Mentor Graphics. Larry was recently an Entrepreneur-in-Residence at Clark University's Graduate School of Management, where he developed and taught a course on Entrepreneurial Communication and Influence. Larry holds an MBA from Clark University in addition to his MS Applied & Engineering Physics from Cornell University and BA Physics from the University of California Berkeley.
Hanan Moller
Director, Customer Solutions Architect @UltraSoC
Hanan joined UltraSoC as Systems Architect in June 2018. His 30 years wealth of experience and expertise in the engineering technology field includes Architect and Engineer roles at Blu Wireless, Imagination Technologies, NVIDIA, ST-Ericsson and Agere Systems, where he architected, specified, designed and verified multiple SoCs for communications and networking systems. Hanan holds an MSc in Electrical Engineering and a BSc in Computer Engineering from the Technion, Israel Institute of Technology, and has 5 patents.