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IEEE TechInsider Webinar: Writing UVM/SystemVerilog Testbenches for Analog/Mixed-Signal Verification

Learn how to write UVM testbenches for analog/mixed-signal circuits. UVM (Universal Verification Methodology) is a framework of standardized SystemVerilog classes to build reusable and scalable testbenches for digital designs, and it can be extended to verifying analog circuits simply by using a fixture module that generates analog stimuli and measures analog responses with Scientific Analog's XMODEL.

Using a digitally-programmable audio bandpass filter as an example, we'll show how to write a UVM testbench that measures the filter's transfer gain at randomly-chosen frequencies, collects the results in a scoreboard until the desired coverage is met, and checks the supply current and bias voltages during power-down with assertions. The webinar will start with an intuitive yet systematic introduction to UVM.

Jun 21, 2022 03:00 PM in Pacific Time (US and Canada)