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Learn UCIe by seeing it in action! This webinar presents the SystemVerilog models for the physical layer (PHY) of a Universal Chiplet Interconnect Express (UCIe) interface, an emerging open industry standard for chiplet interconnects. The presented UCIe PHY model includes both the analog circuits in the electrical layer and digital FSMs in the logical layer and can be simulated efficiently in SystemVerilog, using Scientific Analog’s XMODEL. We invite everyone who is interested in the design and verification of UCIe PHY for chiplets. For analog circuit designers, the presented models will help understand the requirements posed on each circuit block, such as the scaling of bandwidth to support the link speeds ranging from 4 to 32GT/s. For digital verification engineers, the presented testbenches will illustrate how one can perform SystemVerilog-based verification on the systems containing analog circuits. And most importantly, everyone can learn how various components of a UCIe PHY work to realize a high-bandwidth interconnect between chiplets!