webinar register page

Webinar banner
This webinar is for users with a Zoom account. New to Zoom? Sign up free.
Break the kT/C Noise Limit
The sampling kT/C noise is traditionally deemed as a fundamental SNR limit for Nyquist-rate ADCs. To suppress it, the only option is to increase C. Nevertheless, this leads to significant challenges for the ADC input driver and the reference buffer. In fact, the ADC driver and reference buffer are the system bottleneck nowadays. Their power, area, and design complexity can be an order of magnitude higher than the ADC core. Since the root cause of this challenge is the large C, it is highly desirable to break this seemingly fundamental tradeoff between the capacitor size and the kT/C noise.

This talk will introduce two techniques published at ISSCC 2019 and 2020. They can significantly reduce the capacitor size but without incurring a large kT/C noise penalty. The first technique is to operate a SAR ADC in the continuous-time to completely avoid the need for the sampling operation. The second is to cancel the kT/C noise using a novel two-step sampling operation. Both techniques can achieve high resolution with orders of magnitude reduction in the capacitance size, thereby substantially relaxing the requirement for the ADC input driver and reference buffer.

Sep 22, 2020 09:00 AM in Eastern Time (US and Canada)

Webinar logo
* Required information


Nan Sun
Assoc. Professor @University of Texas at Austin
Nan Sun received a B.S. degree from Tsinghua University and a Ph.D. degree from Harvard University. He joined UT Austin in 2011. Dr. Sun received the NSF Career Award in 2013 and the inaugural SSCS New Frontier Award in 2020. He has published 140+ papers, including 25 JSSC papers and 38 ISSCC/VLSI/CICC papers. He serves on the Technical Program Committee of CICC and ASSCC. He is an Associate Editor of TCAS-I and a Guest Editor of JSSC. He also serves as the IEEE Circuits-and-Systems Society Distinguished Lecturer from 2019 to 2020.