As RISC-V evolves over time, the set of ISA features supported by each software ecosystem will also need to evolve over time, and new software ecosystems will be added. To manage this evolution, RISC-V is moving towards a model of regular annual delivery of a coherent set of ISA updates according to an ISA roadmap, and architecture profiles are intended to provide the natural structure for planning, packaging, and releasing these ISA updates.
In this OpenHW TV episode the general structure of RISC-V architecture profiles will be discussed. With reference to the OpenHW CORE-V cores roadmap. Speakers will explain how the CORE-V cores map to the RISC-V profiles along with a focus on the Zce upcoming RISC-V extension, that will be implemented in CV32E41P as a proof of concept project within the OpenHW ecosystem.
The session speakers include: Mark Himelstein, RISC-V International; Jerome Quevremont, Thales Group ; Tariq Kurd, Huawei and the session will be moderated by Davide Schiavone, OpenHW Group.